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_______________general description the max548a/max549a/MAX550A serial, 8-bit voltage- output digital-to-analog converters (dacs) operate from a single +2.5v to +5.5v supply. their ?lsb tue spec- ification is guaranteed over temperature. operating cur- rent (supply current plus reference current) is typically 75? per dac with v dd = 2.5v. in shutdown, the dac is disconnected from the reference, reducing current drain to less than 1?. the max548a/max549a allow each dac to be shut down independently. the 10mhz, 3-wire serial interface is compatible with spi/qspi and microwire interface standards. double-buffered inputs provide flexibility when updat- ing the dacs; the input and dac registers can be updated individually or simultaneously. the max548a is a dual dac with an asynchronous load input; it uses v dd as the reference input. the max549a is a dual dac with an external reference input. the MAX550A is a single dac with an external reference input and an asynchronous load input. the max548a/max549a/MAX550A? low power con- sumption and small ?ax and dip packages make these devices ideal for portable and battery-powered applications. ________________________applications battery-powered systems vcxo control comparator-level settings gaas amp bias control digital gain and offset control ____________________________features ? +2.5v to +5.5v single-supply operation ? ?lsb (max) tue ? power-on reset clears all registers to zero ? low operating current: 150? (max548a/max549a, v ref = +2.5v) 75? (MAX550A, v ref = +2.5v) ? 1? shutdown mode ? 10mhz, 3-wire serial interface compatible with spi/qspi and microwire ? ?ax package?0% smaller than 8-pin so ? independent shutdown of dacs (max548a/max549a) max548a/max549a/MAX550A +2.5v to +5.5v, low-power, single/dual, 8-bit voltage-output dacs in ?ax package ________________________________________________________________ maxim integrated products 1 ldac sclk din 1 2 8 7 v dd outb outa cs gnd dip/ m max top view 3 4 6 5 max548a _________________pin configurations _____________________selector guide 19-1206; rev 0; 3/97 part max548a cpa max548acua max548ac/d 0? to +70? 0? to +70? 0? to +70? temp. range pin-package ? 8 plastic dip 8 ?ax dice* ______________ordering information ordering information continued at end of data sheet. * dice are specified at t a = +25?, dc parameters only. ? contact factory for availability of 8-pin so package. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 max548a max549a number of dacs 2 2 dac reference v dd external feature external asynchronous load dac input MAX550A 1 ?ax package spi and qspi are trademarks of motorola inc. microwire is a trademark of national semiconductor corp. max548aepa max548aeua -40? to +85? -40? to +85? 8 plastic dip 8 ?ax pin configurations continued at end of data sheet. http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , sclk, din, cs , ldac , out_ to gnd ............... -0.3v to 6v ref to gnd ................................................ -0.3v to (v dd + 0.3v) maximum current (any pin) ............................................. 50ma continuous power dissipation (t a = +70 c) plastic dip (derate 9.09mw/ c above +70 c) ............. 727mw max (derate 4.10mw/ c above +70 c) ..................... 330mw operating temperature ranges max5_ _ac_ a ..................................................... 0 c to +70 c max5_ _ae_ a .................................................. -40 c to +85 c storage temperature range ............................. -65 c to +150 c lead temperature (soldering, 10sec) ............................. +300 c max549a max549a/MAX550A for specified performance guaranteed monotonic conditions 16.7 v 2.5 v dd v ref reference input voltage range 0.9 bits 8 n resolution lsb 0.9 dnl differential nonlinearity lsb 1 zce zero-code error lsb 1 fse full-scale error units min typ max symbol parameter max5_ _aeua (note 1) all others max549a/MAX550A max548a MAX550A k 33.3 r out dac output resistance v 0 v ref dac output voltage swing 0 v dd k 33.3 r ref reference input resistance dac code = 55 hex (note 2) max548a/max549a % 0.2 ? r out / r out dac output resistance matching 1 max5_ _aeua (note 1) all others lsb 1 tue total unadjusted error max549a 330 550 150 250 MAX550A 165 275 a 75 125 i ref reference input current dac code = 55 hex (note 3) v dd = v ref = 5.5v v dd = v ref = 2.5v v dd = v ref = 5.5v v dd = v ref = 2.5v v 0.7v dd v ih input high voltage v 0.3v dd v il input low voltage v in = 0v or v dd a 1 i in input current pf 10 c in input capacitance (note 4) static performance reference input dac output digital inputs http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c) timing characteristics (v dd = +2.5v to +5.5v, t a = t min to t max , unless otherwise noted. digital inputs switching from 0v to v dd .) (figure 3) (note 4) note 1: cold temperature specifications (to -40 c) guaranteed by design using six sigma design limits. note 2: worst-case input resistance at ref occurs at dac code 55 hex. note 3: worst-case reference input current occurs at dac code 55 hex. note 4: guaranteed by design. not production tested. note 5: i dd measured with dacs loaded with worst-case dac code 55 hex. cs = high, all digital inputs from 0v to v dd c l = 20pf to 1/2lsb, c l = 20pf v/ s 3.1 s 1.4 voltage-output settling time 4 conditions 50 nv-sec digital feedthrough and crosstalk units min typ max symbol parameter voltage-output slew rate c l = 20pf s wake-up time at power-up 4 v dd = 2.5v v dd = 5.5v supply voltage range outputs unloaded, all inputs = gnd or v dd v dd v 2.5 5.5 supply current (max549a/MAX550A) outputs unloaded, all inputs = gnd or v dd (note 5) a 330 550 i dd supply current (max548a) outputs unloaded, all inputs = gnd or v dd ; v dd = 5.5v i dd a 0.3 10 v dd = 5.5v v dd = 2.5v shutdown current shutdown mode a 0.3 150 250 80 50 sclk period t cp cs high to ldac low ns t csld ns max548a/MAX550A only 5 v dd high to cs low s 50 ldac pulse width low t l dac ns max548a/MAX550A only 40 cs pulse width high t csw ns 20 t csh1 ns v dd = 5.5v 10 30 t dh cs high to sclk high setup ns t css1 ns 10 delay, sclk high to cs high v dd = 2.5v v dd = 5.5v 30 cs low to sclk high setup t css0 ns 30 din to sclk high setup t ds ns 0 din to sclk high hold v dd = 2.5v 40 sclk pulse width low t cl ns parameter symbol min typ max units conditions 40 sclk pulse width high t ch ns dynamic performance power supplies 10 sclk high to cs low hold t csh0 ns http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 4 _______________________________________________________________________________________ __________________________________________ t ypical operating characteristics (v dd = v ref = 2.5v, r l = 1m , c l = 15pf, t a = +25 c, unless otherwise noted.) -60 -20 20 100 operating current per dac vs. temperature 75.0 74.6 149.8 150.2 max548a-550a toc-01 temperature (?) operating current per dac ( m a) 60 149.4 75.4 v dd = v ref = 5.0v v dd = v ref = 2.5v -60 -20 20 100 shutdown current vs. temperature 36 32 28 160 200 240 max548a-550a toc-02 temperature (?) shutdown current (na) 60 120 40 v dd = v ref = 5.0v v dd = v ref = 2.5v -50 1k 10k 100k 1m 10m max549a/MAX550A reference small-signal frequency response -40 10 0 max548a-550a toc-03 frequency (hz) relative output (db) -20 -30 -10 dac code = ff hex v dd = 5v v ref = 2vp-p sine wave v dd = 2.5v v ref = 100mvp-p sine wave 0 -100 10 1m 100k 10k 1k 100 max549a/MAX550A reference ac feedthrough vs. frequency -60 -80 max548a-550a toc-04 frequency (hz) relative output (db) -40 -20 v ref = 1vp-p sine wave dac code = 00 hex digital feedthrough sclk, 5v/div out, 50mv/div 200ns/div max548a-550a toc-05 settling time (falling) out, 1v/div 2 m s/div max548a-550a toc-06 cs, 5v/div dac code ff hex to 00 hex http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package _______________________________________________________________________________________ 5 output glitch filtering out, 50mv/div, c l = 0pf out, 50mv/div, c l = 100pf out, 50mv/div, c l = 220pf 5 m s/div out, 50mv/div, c l = 1000pf max548a-550a toc-07 cs, 5v/div code = 00 hex _____________________________ t ypical operating characteristics (continued) (v dd = v ref = 2.5v, r l = 1m , c l = 15pf, t a = +25 c, unless otherwise noted.) settling time (rising) out, 1v/div 2 m s/div max548a-550a toc-08 cs, 5v/div dac code 00 hex to ff hex ______________________________________________________________ pin description ground 1 1 1 gnd dac a output voltage 2 2 outa chip-select input. a logic low on cs enables serial data to be clocked into the input shift register. programming commands are executed at cs ? rising edge. 3 3 3 cs dac output voltage 2 out serial-clock input. data is clocked in on sclk? rising edge. 5 5 5 sclk dac b output voltage 6 7 outb load dac input. after cs goes high and if programmed by the control word, a falling edge on ldac updates the dac latch(es). connect ldac to v dd if unused. 6 6 ldac serial-data input. data is clocked into the 16-bit input shift register on sclk? rising edge. 4 4 4 din positive power supply (+2.5v to +5.5v) 8 8 8 v dd external reference voltage input for dac(s) 7 7 ref max548a max549a MAX550A name function pin http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 6 _______________________________________________________________________________________ _______________ detailed description analog section the max548a/max549a/MAX550A are 8-bit, voltage- output digital-to-analog converters (dacs). the max548a/max549a are dual dacs, and the MAX550A is a single dac. each dac consists of an r-2r ladder network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied ref - erence voltage (figure 1). the dacs feature double-buffered inputs and unbuffered outputs. the max549a/MAX550A require an external reference. the max548a? reference inputs are internally connected to v dd . the power-supply range is from +2.5v to +5.5v. reference input the voltage applied at ref (v dd for the max548a) sets the full-scale output for all the dacs and may range from +2.5v to v dd . the ref input resistance is code dependent, with the lowest value occurring with code 01010101 (55 hex). to minimize inl errors, the refer - ence voltage source should have less than 3 output impedance. dac output the max548a/max549a/MAX550A contain dacs with unbuffered outputs; each output connects directly to an r-2r ladder. typical output impedance is 33.3k . this configuration minimizes power consumption and reduces offset errors. for highest accuracy, apply high resistive loads (1m and up). lower resistive loads can be driven, but output loading increases full-scale error. the magnitude of the expected error is the ratio of the dac output resistance to the dc load resistance at the output. typically, an energy pulse is coupled into the dac out - put on cs ? rising edge. since each dac output is unbuffered, connecting a small capacitor (200pf to 1000pf) from the output to ground creates a lowpass filter that effectively suppresses the pulse for sensitive applications (see typical operating characteristics ). shutdown mode when the max548a/max549a/MAX550A are in shut - down mode, the r-2r ladder disconnects from the refer - ence source. the max549a/MAX550A supply current does not change, but the ref input current decreases to less than 1 a. this allows the externally applied system reference to remain active with minimal power consumption. the max548a supply current also decreases to less than 1 a in shutdown mode. when the max548a/max549a/MAX550A exit shutdown mode, recovery time is equivalent to the dac? settling time. serial interface the serial interface is spi/qspi and microwire compati - ble. an active-low chip select ( cs ) enables the input shift register to receive data from the serial input (din). data is clocked into the shift register on the rising edge of the serial-clock signal (sclk). the clock frequency can be as high as 10mhz. transmit data msb first in one 16-bit word or two 8-bit bytes. the write cycle can be segmented to allow two 8-bit-wide transfers when cs remains low. after all 16 bits are clocked into the input shift register, a rising 2r r r r r 2r 2r 2r 2r 2r ref gnd note: switch positions shown for dac code ff hex. dac_ register out_ msb lsb gnd 2r r r r 2r 2r 2r 2r figure 1. dac simplified circuit diagram http://
edge on cs programs the dac. the input registers can be loaded independently or simultaneously without updating the dac registers. this allows both dac reg - isters to be updated simultaneously with different digital values. the dac outputs reflect the data stored in the dac registers. ldac can be used to asynchronously update the dac registers independently of cs (max548a/MAX550A). with c1 set high, setting c0 in the control word forces the dac register(s) to be updated on ldac ? falling edge, rather than cs ? rising edge (table 1). initialization the max548a/max549a/MAX550A have an internal power-on reset. at power-up, all internal registers are reset to zero; therefore, an initialization write sequence is not necessary. serial-input data format and control codes the control byte determines which input registers/dac registers are updated (table 1). the dac input regis - ters are updated on the rising edge of cs . the dac registers can be updated on cs ? rising edge or on ldac ? falling edge after cs goes high. bit c0 of the control byte determines how the dac registers are updated for the max548a/MAX550A. the max549a has no ldac pin; the dac registers are always up- dated on cs ? rising edge (c0 in the control byte has no effect). tables 2, 3, and 4 list the serial-input command format for the max548a, max549a, and MAX550A, respec - tively. the 16-bit input word consists of an 8-bit control byte and an 8-bit data byte. the control byte is not decoded internally. every control bit performs one max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package _______________________________________________________________________________________ 7 ub3 x unassigned bit 3 c2 1 power-down mode c2 0 power-up mode c1 1 dac register load operation enabled c0 1 dac register updated on ldac ? falling edge (max549a = don? care) c0 0 dac register updated on cs ? rising edge c1 0 dac register load operation disabled a1 1 address dac b (MAX550A = don? care) a0 1 address dac a a0 ub2 0 do not address dac a d6 dac data bit 6 d4 x dac data bit 4 d5 unassigned bit 2 state dac data bit 5 d7 dac data bit 7 (msb) a1 0 do not address dac b (MAX550A = don? care) d2 operation dac data bit 2 d0** data byte dac data bit 0 (lsb) d1 dac data bit 1 d3 dac data bit 3 table 1. control-byte/input-word bit definitions x = don? care * clocked in first ** clocked in last ub1* x unassigned bit 1 control byte bit name http://
max548a/max549a/MAX550A function. data is clocked in starting with unassigned bit 1 (ub1), followed by the remaining control bits and the dac data byte. the data byte? lsb (d0) is the last bit clocked into the input register (figure 2). table 5 is an example of a 16-bit input word that per - forms the following functions: loads 80 hex (128 decimal) into the dac input regis - ter (dac a for the max548a/max549a) updates the dac register(s) on cs ? rising edge. table 6 shows how to calculate the output voltage based on the input code. figure 3 gives detailed timing information. +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 8 _______________________________________________________________________________________ din sclk 1 8 9 16 ldac max548a/ MAX550A only ub1 ub2 ub3 c2 c1 c0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 optional pause cs instruction executed figure 2. serial-interface timing diagram cs sclk din t ds t dh t cl t ch t css0 t csh0 t ldac t csw t csh1 t css1 t csld ldac figure 3. detailed serial-interface timing diagram http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package _______________________________________________________________________________________ 9 table 2. max548a serial-interface programming commands command (commands executed on cs ? rising edge) ldac commands loading input register(s) only x unassigned operation x xxxxxxxx 0 0 x x x 1 x x unassigned command x xxxxxxxx 0 0 x 0 x 0 x control byte loaded first loaded last ub1 pin 6 d7........d0 a0 a1 c0 c1 ub3 c2 ub2 x load dac b input register and update both dac registers. dac a input register unchanged. 0 8-bit dac data x load dac a input register and update both dac registers. dac b input register unchanged. 0 8-bit dac data 0 1 1 1 x 0 x 1 0 1 1 x 0 x update both dac registers with current contents of their input registers. both input registers unchanged. 0 0 0 1 1 x 0 x x x load both dac input registers and update both dac registers. x 8-bit dac data 1 1 0 1 x 0 x x load dac b input register and update both dac registers. dac a input register unchanged. x 8-bit dac data 0 1 0 1 x 0 x x load both dac input registers. both dac regis - ters unchanged. x 8-bit dac data 1 1 x 0 x 0 x x load dac b input register. dac a input register and both dac registers unchanged. x 8-bit dac data 0 1 x 0 x 0 x x load dac a input register and update both dac registers. dac b input register unchanged. x 8-bit dac data 1 0 0 1 x 0 x x load dac a input register. dac b input register and both dac registers unchanged. update both dac registers with current contents of their input registers. both input registers unchanged. x x 8-bit dac data xxxxxxxx 1 0 0 0 x 0 0 1 x 0 x 0 x x x unassigned commands data byte xxxxxxxx commands updating dac register(s) x load both dac input registers and update both dac registers. 0 8-bit dac data 1 1 1 1 x 0 x commands utilizing the asynchronous load function x after cs ? rising edge and on ldac ? falling edge, update both dac registers with current contents of their input registers. both input regis - ters unchanged. 1 xxxxxxxx 0 0 1 1 x 0 x x load dac a input register. after cs ? rising edge and on ldac ? falling edge, update both dac registers. 1 8-bit dac data 1 0 1 1 x 0 x x load dac b input register. after cs ? rising edge and on ldac ? falling edge, update both dac registers. 1 8-bit dac data 0 1 1 1 x 0 x x load both dac input registers. after cs ? rising edge and on ldac ? falling edge, update both dac registers. 1 8-bit dac data 1 1 1 1 x 0 x http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 10 ______________________________________________________________________________________ table 2. max548a serial-interface programming commands (continued) commands for powering down x 1 x 0 x 1 0 control byte 8-bit dac data x load dac b input register and power down dac b. dac a registers unchanged. x x 1 x 0 x 1 1 8-bit dac data x load both dac input registers and power down both dacs. both dac registers unchanged x x 1 x 1 0 1 0 8-bit dac data x load dac b input register, power down dac b, and update both dac registers. dac a input register unchanged. x x = don? care x 1 x 1 0 0 1 8-bit dac data x load dac a input register, power down dac a, and update both dac registers. dac b input register unchanged. x x 1 x 0 x 0 1 8-bit dac data x load dac a input register and power down dac a. dac b registers unchanged. x x 1 x 1 0 1 1 8-bit dac data x load both dac input registers, power down both dacs, and update both dac registers. x x 1 x 1 1 0 1 8-bit dac data 0 load dac a input register, power down dac a, and update both dac registers. dac b input register unchanged. x x 1 x 1 1 1 0 8-bit dac data 0 load dac b input register, power down dac b, and update both dac registers. dac a input register unchanged. x x 1 x 1 1 1 1 8-bit dac data 0 load both dac input registers and power down both dacs. update both dac registers. x x 1 x 1 1 0 1 8-bit dac data 1 load dac a input register and power down dac a. while powered down, on ldac ? falling edge, update both dac registers. dac b input register unchanged. x x 1 x 1 1 1 0 8-bit dac data 1 load dac b input register and power down dac b. while powered down, on ldac ? falling edge, update both dac registers. dac a input register unchanged. x x 1 x 1 1 1 1 8-bit dac data 1 load both dac input registers and power down both dacs. while powered down, on ldac ? falling edge, update both dac registers. x command (commands executed on cs ? rising edge) ldac data byte loaded last loaded first pin 6 d7........d0 ub1 a0 a1 c0 c1 c2 ub3 ub2 commands powering down and loading input register(s) only commands powering down and updating dac register(s) commands powering down and utilizing the asynchronous load function http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package ______________________________________________________________________________________ 11 table 3. max549a serial-interface programming commands data byte unassigned command x x x x x 0 x 1 0 x x 0 0 0 1 x 0 x 0 x 1 0 xxxxxxxx 8-bit dac data loaded first update both dac registers with current contents of their input registers. both input registers unchanged. load dac a input register. dac registers unchanged. x x 0 x 1 x 0 1 x 0 x 1 x 1 0 8-bit dac data load dac a input register and update both dac registers. dac b input register unchanged. x 1 x 0 x x 0 1 x 1 x 0 x 1 0 8-bit dac data load dac a input register and power down dac a. dac b input register and both dac registers unchanged. x 8-bit dac data load dac b input register and power down dac b. dac a input register and both dac registers unchanged. x loaded last x 1 x 0 x 1 1 8-bit dac data load both dac input registers and power down both dacs. both dac registers unchanged. x 8-bit dac data load dac b input register. dac registers unchanged. x x 0 x 0 x 1 1 8-bit dac data load both dac input registers. dac registers unchanged. x 8-bit dac data load dac b input register and update both dac registers. dac a input register unchanged. x x 0 x 1 x 1 1 8-bit dac data load both dac input registers and update both dac registers. x command (commands executed on cs ? rising edge) control byte ub2 c2 ub3 c1 c0 a1 a0 d7........d0 ub1 x x x 0 x 0 0 xxxxxxxx unassigned command x commands loading input register(s) only commands updating dac register(s) commands powering down and loading input register(s) only x = don? care commands powering down and updating dac register(s) x 1 x 1 x 0 1 8-bit dac data load dac a input register, power down dac a, and update both dac registers. dac b input register unchanged. x x 1 x 1 x 1 0 8-bit dac data load dac b input register, power down dac b, and update both dac registers. dac a input register unchanged. x x 1 x 1 x 1 1 8-bit dac data load both dac input registers, power down both dacs, and update both dac registers. x http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 12 ______________________________________________________________________________________ table 4. MAX550A serial-interface programming commands commands loading dac register commands loading input register only unassigned commands loaded last loaded first ldac control byte command (commands executed on cs ? rising edge) x update dac register with current contents of input register. input register unchanged. 0 0 x 1 1 x 0 x xxxxxxxx x load dac input register and update dac register. 0 8-bit dac data 1 x 1 1 x 0 x xxxxxxxx x load dac input register and update dac register. x 8-bit dac data 1 x 0 1 x 0 x ub1 pin 6 d7........d0 a0 a1 c0 c1 ub3 c2 ub2 x update dac register with current contents of input register. input register unchanged. x 0 x 0 1 x 0 x x load dac input register. dac register unchanged. x 8-bit dac data 1 x x 0 x 0 x x unassigned operation x xxxxxxxx 0 x x x x x 1 x unassigned command x xxxxxxxx 0 x x 0 x 0 x data byte commands utilizing the asynchronous load function x after cs ? rising edge and on ldac ? falling edge, update dac register with current contents of input register. input register unchanged. 1 xxxxxxxx 0 x 1 1 x 0 x x load dac input register. after cs ? rising edge and on ldac ? falling edge, update dac register. 1 8-bit dac data 1 x 1 1 x 0 x command powering down and loading input register only x load dac input register and power down dac. x 8-bit dac data 1 x x 0 x 1 x commands powering down and updating dac register x load dac input register, power down dac, and update dac register. x 8-bit dac data 1 x 0 1 x 1 x x load dac input register, power down dac, and update dac register. 0 8-bit dac data 1 x 1 1 x 1 x command powering down and utilizing the asynchronous load function x load dac input register and power down dac. while powered down, on ldac ? falling edge, update dac register. 1 8-bit dac data 1 x 1 1 x 1 x table 5. example input word x = don? care x = don? care ub2 x c2 0 ub3 x c0 0 control byte a0 1 loaded first a1 0 c1 1 d6 0 d4 0 d5 0 d2 0 data byte d0 0 loaded last d1 0 d3 0 d7 1 ub1 x http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package ______________________________________________________________________________________ 13 table 6. analog output vs. code microprocessor interfacing the max548a/max549a/MAX550A serial interface is spi/qspi and microwire compatible. for spi/qspi, clear the cpol and cpha bits (cpol = 0 and cpha = 0). cpol = 0 sets the clock idle state to zero, and cpha = 0 changes data at sclk? falling edge. this is the microwire default condition. if a serial port is not avail - able on your microprocessor, three bits of a parallel port can be used to emulate a serial port by bit manipulation. operate the serial clock only when necessary, to mini - mize digital feedthrough at the dac registers. __________ applications infor mation power-supply and ground considerations connect gnd to the highest quality ground available. bypass v dd with a 0.1 f to 0.22 f capacitor to gnd. the reference input can be used without bypassing. however, for optimum line/load-transient response and noise performance, bypass the reference input with a 0.1 f to 4.7 f capacitor to gnd. careful pc board layout minimizes crosstalk in dac regis - ters, the reference, and the digital inputs. separate analog traces by running ground traces between them. make sure that high-frequency digital lines are not routed parallel to analog lines. ac considerations digital feedthrough high-speed data at any of the digital input pins can couple through a dac? internal stray package capaci - tance and cause noise (digital feedthrough) at the dac output, even though ldac and/or cs are held high (see typical operating characteristics ). test digital feedthrough by holding ldac and/or cs high and tog - gling the digital inputs from all 1s to all 0s. analog feedthrough due to internal stray capacitance, higher frequency analog input signals at ref can couple to the output, even when the input digital code is all 0s. this condition is shown in the max549a/MAX550A reference ac feedthrough vs. frequency graph in the typical operating characteristics . test analog feedthrough by setting all dac outputs to 0v and sweeping ref. note: 1lsb = v ref x 2 -8 = v ref (1 / 256); analog output = +v ref (i / 256), where i = integer value of digital input. _____________________________________________ pin configurations (continued) outb sclk din 1 2 8 7 v dd ref outa cs gnd dip/ m max top view 3 4 6 5 max549a ldac sclk din 1 2 8 7 v dd ref out cs gnd dip/ m max 3 4 6 5 MAX550A analog output (v) +v ref (255 / 256) +v ref (129 / 256) 0 0 0 0 1 0 0 1 +v ref (128 / 256) = +v ref / 2 +v ref (127 / 256) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 d6 1 1 d4 1 +v ref (1 / 256) d5 1 0 d2 1 0 dac contents d0 1 0 d1 1 0 d3 1 0 d7 1 0 0 0 0 0 0 0 0 1 0 0 0 http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package 14 ______________________________________________________________________________________ transistor count: 1562 _________________________________________________________ functional diagram _ or dering infor mation (continued) ___________________ chip infor mation dac a input register dac a register dac a r-2r ladder sclk din outa outb ref max549a/ MAX550A only v dd max548a only max548a/ max549a only input shift register and control 8 v dd cs max548a max549a MAX550A gnd ldac max548a/ MAX550A only dac b input register dac b register dac b r-2r ladder 8 8 8 8 8 part max549a cpa max549acua max549ac/d 0 c to +70 c 0 c to +70 c 0 c to +70 c temp. range pin-package 8 plastic dip 8 max dice* max549aepa max549aeua -40 c to +85 c -40 c to +85 c 8 plastic dip 8 max MAX550A cpa MAX550Acua MAX550Ac/d 0 c to +70 c 0 c to +70 c 0 c to +70 c 8 plastic dip 8 max dice* MAX550Aepa MAX550Aeua -40 c to +85 c -40 c to +85 c 8 plastic dip 8 max * dice are specified at t a = +25 c, dc parameters only. http://
max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package ______________________________________________________________________________________ 15 ________________________________________________________ package infor mation pdipn.eps http://
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. max548a/max549a/MAX550A +2.5v to +5.5v , low-power , single/dual, 8-bit v oltage-output dacs in max package maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. ___________________________________________ package infor mation (continued) 8lumaxd.eps http://

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